How to generate a .dat file for verilator_coverage?

I've started to familiarize myself with cocotb and I'm having trouble.

I wrote a simple test like this:

@cocotb.test()async def add_test(dut):    dut._log.info("Running add test!")    c = Clock(dut.clk, 10, 'ns')    await cocotb.start(c.start())    a = 1    b = 2    for cycle in range(10):       a += 1       b += 1       await RisingEdge(dut.clk)       dut.exu2ialu_main_op1_i <= a       dut.exu2ialu_main_op2_i <= b       dut.exu2ialu_cmd_i <= 4        await RisingEdge(dut.clk)       assert dut.ialu2exu_main_res_o == (a+b)

and threw together a simple makefile:

VERILOG_INCLUDE_DIRS = $(PWD)/includeVERILOG_SOURCES = $(PWD)/myalu.sv TOPLEVEL=scr1_pipe_ialu  # the module name in your Verilog or VHDL fileMODULE=test # the name of the Python test fileinclude $(shell cocotb-config --makefiles)/Makefile.sim

The first problem is that the first run of make SIM=verilator crashes and judging by the log is due to a large number of warnings(11). On subsequent runs everything is fine, I attribute this to the fact that sim_build is being built, but I would like to understand if the crash can be avoided.

The second problem is that I was recommended to analyze the test coverage with the verilator_coverage utility, which should accept a .dat file, but it is not generated. I tried to fix this with the command make SIM=verilator COVERAGE=1 , but that did not work.